Work with IP/SoC architecture to study design feasibilities meeting PPA requirements. Create Micro-architecture specification (MAS), perform RTL coding based on MAS using best RTL coding practices, and integrate the RTL into the IP/SoC. Perform RTL code review, apply tools to formally check/fix RTL against various design rules. Perform design verification for critically important design blocks. Work with the verification team to define test-plan, debug/fix failures, analyze coverage. Cooperate with Synthesis, DFT, STA, PnR teams to solve issues related to in-charged IP. Support Emulation, FPGA prototype, functional ATE, and silicon validation teams.
BS/MS in Computer Science, Electrical Engineering, or related fields and 10+ years of related professional experience. Proven track record of digital IP design from concept to successful ASIC/SoC project TOs. Very familiar with digital IC design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design tools. Hands-on behavioral and RTL coding experience, Verilog/SV preferred. Strong knowledge of verification methodology, logic synthesis and timing analysis. Excellent problem solving skills and out-of-the-box thinking to oversee design failures. Very good at documentation and communication skills using English. Experiences in UVM verification methodology is a plus Experiences in Ethernet/DDR/SRAM/USB/PCIe/USB/SAS/SATA IF is a plus. Experiences in NVMe, NVMoF, ARM-based SoC, Emulation, FPGA prototype is a plus.
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.