Design Verification Engineer (VLSI)
Designer Testing Test Plan Writing Scripting
Benefit
Full social insurance
Flexible working time
Salary review
Travel/company trips
Laptop/desktop for works
Performance bonus
Extra health insurance
13th month salary
Others
Work-from-home policy
Job Overview And Responsibility
Full chip test plan development/modification Testbench development/modification Test case development, coding, execution, bug analysis Regressions, coverage analysis Verification closure To ensure process compliance in the assigned module| and participate in technical discussions/review. To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Required Skills and Experience
Bachelors/Master’s degree in Electronics /Electrical Engineering with 5+ years’ experience in verification. Good understanding of ASIC/SoC life cycle. Experience with Full chip test plan development/modification. Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure. Experience with Gate level simulations. Experience in scripting. Should have participated in multiple ASIC/SoC verification till tape out stage. Be able to use English in working communication. Required Skills: Design Verification - VLSI- System Verilog
Why Candidate should apply this position
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