Design Verification Engineer (VLSI)
Designer Testing Test Plan Writing Scripting
福利厚生
完全な社会保険
柔軟な勤務時間
人事考課
社員旅行
業務用ノートパソコン/デスクトップ
実績に応じた追加の報酬
追加の健康保険
13ヶ月目の給与
その他
在宅勤務ポリシー
職務概要
Full chip test plan development/modification Testbench development/modification Test case development, coding, execution, bug analysis Regressions, coverage analysis Verification closure To ensure process compliance in the assigned module| and participate in technical discussions/review. To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
必要なスキルと経験
Bachelors/Master’s degree in Electronics /Electrical Engineering with 5+ years’ experience in verification. Good understanding of ASIC/SoC life cycle. Experience with Full chip test plan development/modification. Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure. Experience with Gate level simulations. Experience in scripting. Should have participated in multiple ASIC/SoC verification till tape out stage. Be able to use English in working communication. Required Skills: Design Verification - VLSI- System Verilog
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