[ĐN] Analog Layout Design Engineer

職務概要

Candidates do not have to have experience on all the tasks below, there will be trainings to new engineers to adapt with Synopsys design and flows. - Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees... - Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics - Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield. - Participate in building and enhancing layout flow for faster, higher quality design process. - Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM - Do PERC verification for ESD/LUP checks - Complete all design quality checks and data quality checks - Work with Place and Route engineer to integrate analog layouts into top level. - Work with Package team to ensure the integration of top die and package - Do design reviews across global team - May collaborate in package design (interposer design, RDL design) - Work closely with design team in Viet Nam, USA, Canada and other countries to ensure the success of the whole product. - May join research programs to implement new ideas for future products and flows - May lead a layout team to complete a full design block - Mentor junior layout engineers or interns