Design Verification Engineers (VLSI)
ClosedEnginering
勤務地
総空席数
福利厚生
13ヶ月目の給与
柔軟な勤務時間
完全な社会保険
その他
人事考課
社員旅行
業務用ノートパソコン/デスクトップ
実績に応じた追加の報酬
追加の健康保険
在宅勤務ポリシー
職務概要
- Full chip test plan development/modification - Testbench development/modification - Test case development, coding, execution, bug analysis - Regressions, coverage analysis - Verification closure - To ensure process compliance in the assigned module and participate in technical discussions/review. - To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
必要なスキルと経験
- Bachelors/Master’s degree in Electronics /Electrical Engineering with 3+ years’ experience in verification. - Good understanding of ASIC/SoC life cycle. - Experience with Full chip test plan development/modification. - Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, and Verification closure. - Experience with Gate level simulations. - Experience in scripting. - Should have participated in multiple ASIC/SoC verifications till the tape-out stage. - Be able to use English in working communication.
この求人に応募する理由
- 18 paid leaves/year (12 annual leaves and 6 personal leaves) - Insurance plan based on full salary + 13th month salary + Performance bonus - Meal allowance of 730,000 VND/month - 100% full salary and benefits as an official employee from the 1st day of working - Medical benefit for employee and family - Working in a fast-paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries) - Internal training (Technical & Functional & English)
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