Senior Digital Test Chip Engineer

職務概要

You will be part of a team responsible in digital IP development including RAM, ROM and digital libraries. You will have the responsibility to specify and design digital Integrated Circuit embedding the developed digital IPs to allow their Silicon validation in the context of ISO26262 environment. Your Role: 1. Specifications of test chips allowing the silicon measurement of all parameters of RAM, ROM and digital libraries e.g., leakage current, power consumption, access time, peak current, … Propose design solution allowing the most accurate measurements. 2. Develop digital Integrated Circuit including the full development flow RTL, Synthesis, DFT insertion, Place and Route, Physical Verification (DRC, LVS), RTL and gate level Simulation. 3. Generate functional Test patterns e.g., ATPG and custom test patterns. Define by simulation limits for parametric tests with Static Timing Analysis reports, Power Analysis reports 4. Evaluate new DFT methodology e.g., Cell-Aware Test patterns 5. Documentation relative to Test Chips datasheet and test datasheet 6. Interface with Test Engineers, organize debug session for issue analysis 7. Contribute to QA flow for digital IP usage. Interface with digital IP designers. Report and document improvement for better digital IP integration/usage. 8. Specify and design Test Qualification Vehicle for digital IP and technology process qualification and demonstrator to highlight the capability of the technology and digital IP portfolio.