Design Verification Engineer

Enginering Research Design Development Problem Solving Debugging

Icon salary Salary
Negotiable
Icon Location Location
Ho Chi Minh

Benefits

Extra health insurance Extra health insurance
Flexible working time Flexible working time
Full social insurance Full social insurance
Salary review Salary review
Travel/company trips Travel/company trips
Laptop/desktop for works Laptop/desktop for works
Performance bonus Performance bonus

Job Overview And Responsibility

- Develop and review verification plan - Create testcase and perform RTL verification using SystemVerilog, UVM - Debug the failing testcase, work with RTL design team analyze the root-cause - Perform and evaluate verification regression - Perform gate-level simulation with SDF back-annotation

Required Skills and Experience

- BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. - 2+ years of experience in Design Verification - Familiar with design verification flow at IP or SoC level - Good debugging capability and problem-solving skills

Why Candidate should apply this position

Opportunities: - SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team - Professional, innovative, fair and fun working environment. Strong culture company. - Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table-tennis, Badminton, Yoga, Zumba … - Dedicated support from company for team building, social activities: Team trip, Family Day… - Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon. - Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications. - Clear career path of self-development to either Technical Expert or Design Leader/Manager - Insurance - Travel - Team building - Birthday celebration - Promotion - Bonus - Healthcare - Training - Days off on Saturday and Sunday

Preferred skills and experiences

- Knowledge of SystemVerilog, UVM, and complex module testbench is a big plus - Knowledge of Analog Mixed Signal design, High-Speed Interface IP is a big plus

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Peter Lim

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