Senior Digital Test Chip Engineer
Enginering
Salary
Location
Benefits
Extra health insurance
Free lunch and Snacks
Performance bonus
Others
Work-from-home policy
Job Overview And Responsibility
You will be part of a team responsible in digital IP development including RAM, ROM and digital libraries. You will have the responsibility to specify and design digital Integrated Circuit embedding the developed digital IPs to allow their Silicon validation in the context of ISO26262 environment. Your Role: 1. Specifications of test chips allowing the silicon measurement of all parameters of RAM, ROM and digital libraries e.g., leakage current, power consumption, access time, peak current, … Propose design solution allowing the most accurate measurements. 2. Develop digital Integrated Circuit including the full development flow RTL, Synthesis, DFT insertion, Place and Route, Physical Verification (DRC, LVS), RTL and gate level Simulation. 3. Generate functional Test patterns e.g., ATPG and custom test patterns. Define by simulation limits for parametric tests with Static Timing Analysis reports, Power Analysis reports 4. Evaluate new DFT methodology e.g., Cell-Aware Test patterns 5. Documentation relative to Test Chips datasheet and test datasheet 6. Interface with Test Engineers, organize debug session for issue analysis 7. Contribute to QA flow for digital IP usage. Interface with digital IP designers. Report and document improvement for better digital IP integration/usage. 8. Specify and design Test Qualification Vehicle for digital IP and technology process qualification and demonstrator to highlight the capability of the technology and digital IP portfolio.
Required Skills and Experience
• Master or higher in Electronics Engineering. • Minimum 5 years of working experience in developing digital Integrated Circuit. Mandatory Back-End digital design skills (Place and Route, Physical Verification). Front-End digital design (RTL) is an advantage. • Good knowledge and understanding of digital circuits • Experience with Place and Route tool for floor planning, CTS and routing and Physical Verification (LVS, DRC) • Timing Analysis and Power Analysis • Synthesis and DFT insertion • RTL design and verification experience is a plus • Scripting (TCL, perl, python) for automatization
Why Candidate should apply this position
You will be part to the team developing state-of-the-art digital libraries allowing best-PPA digital design mainly dedicated for automotive market. - Relocation assistance for expat. - Relocation allowance – 1 month of salary - Home passage – return trip tickets for employee, spouse, and kids to home country once a year - Children international education fee by employer - Career development and training - Work-life balance - International secondment program - Pension provisions - Bonus schemes - Health and prevention programs - Cafeteria and meal subsidy - Free parking - Hybrid working (1 day WFH per week)
Preferred skills and experiences
• RTL design and verification experience is a plus
Report to
Global Manager based in France
Interview process
Interview with Team Lead/ Manager in Kuching and General Manager in EU (Can split into 2 separate interviews based on schedule)
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